DECIDER: A System for Hierarchical Test Pattern Generation

A hierarchical test pattern generation system that uses register-transfer level VHDL and gate-level EDIF netlist descriptions as inputs is presented in current paper. The main novelty of the hierarchical ATPG tool lies in the fact that it implements internal representation of mixed-level (register-transfer and structural levels) decision diagram models. The system includes appropriate interfaces to synthesize Decision Diagram (DD) models, a DD based test pattern generator and a fault simulator to evaluate the quality of the generated tests. In the paper, the structure of the system is presented. Additionally, representation of different design abstraction levels using decision diagrams is explained. The performance of the system is compared to other state-of-the-art tools for sequential circuit test generation. Experiments show that the proposed method allows to reach high fault coverages for circuits with complex sequential structures in a very short time.